Whose power reduction is better. Clock gating or Data enable?

by Trung anh nguyễn thành   Last Updated June 30, 2020 03:25 AM

I am comparing Clock Gating (ECG) and Data enable methods in term of power reduction. Both can save power.

But which one is better? I tried these 2 methods in a small design ( a d flipflop ) to a larger one (8-bit data register) and measured their power dissipation. The results always show that Data enable consumes less power than Clock Gating.

Then why is Clock Gating used so often for power reduction? Is there any cases when Clock Gating consumes more power than Data enable ?

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Tags : power vlsi

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