Verlog to Logic Diagram

by bieaisar   Last Updated January 14, 2018 09:25 AM

I am trying to draw the logic diagram of this Verilog Code of a counter.

module CNT1 (Q, QN, To, CLK, D, L, RB, Ti); output Q, QN, To; input CLK, D, L, RB, Ti; reg q, tout; function mux; input [3:0] in; input [1:0] s; case(s) 2'b00: mux=in[0]; 2'b01: mux=in[1]; 2'b10: mux=in[2]; 2'b11: mux=in[3]; endcase endfunction always @(RB) begin if (!RB) assign q=1'b0; else deassign q; end always @(posedge CLK) q=mux({D,D,~q,q},{L,Ti}); always @(Ti or q) tout=Ti&q; assign To=tout; assign Q=q; assign QN=~q; endmodule

I have drawn this but i am not sure. Do you have a suggestion related to logic diagram of this code? Thank you.

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